In high speed static RAM systems such as, for example, one disclosed in U.S. Pat. No. 4,665,508 assigned to the assignee of, the present invention, the typical combination of a high bit line capacitance and a relatively low level of bit line charging current necessitates a low bit line voltage swing. Accordingly, conventional static RAM designs have employed relatively complex and power consumptive circuitry to provide sufficient signal magnification. Even so, sense amplifier gain has been a limiting factor in the speed of memory operations, e.g., reading data out of memory cells. That is, for a given level of amplification a minimum bit line swing voltage must be provided in order to develop a signal of sufficient magnitude to permit proper operation of adjoining circuitry.
The response time, t, for developing a voltage swing, V, is proportional to the voltage, i.e., EQU V=It/C
where I is the bit line charging current and C is the bit line capacitance. The desire in the art is to minimize the response time in order to provide higher speed memory operation. In the process of increasing the density of static RAM devices it is also desirable to minimize power dissipation as well as the area occupied by the circuit components.
In accordance with the present invention there is provided a digital memory system of the type which includes an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell. The system overcomes several limitations associated with the above mentioned high speed circuits by including a bit line pull-up transistor positioned to function as a current source for the bit line and as a load device for the amplifier transistor.
In a general form the system includes a column of memory cells and a plurality of word lines connected for selecting a memory cell. A bit line is connected to each memory cell in the column and a bit line pull-up transistor having first, second and third terminals is arranged to form a current source at the second terminal. First and second source/drain electrodes of an amplifier transistor are connected to the second terminal of the pull-up transistor and the bit line respectively. The gate electrode of the amplifier transistor is connected to receive a bias voltage. An amplified bit line signal corresponding to the state of a selected memory cell is available at an output node between the pull-up and amplifier transistors.
The preferred embodiment of the memory system includes first and second bit lines connected to each memory cell in the column. A bit line pull-up transistor and an amplifier transistor are associated with each bit line as described above. An output node between the first pull-up and amplifier transistors provides an amplified bit line signal corresponding to the state of a selected memory cell while a second output node between the second pull-up transistor and the second amplifier transistor provides an amplified bit line signal corresponding to the inverted state of a selected memory cell.
According to the preferred embodiment the gate electrode of the first amplifier transistor is connected to the second source/drain electrode of the second amplifier transistor and the gate electrode of the second amplifier transistor is connected to the second source/drain electrode of the first amplifier transistor. These gate connections provide gate to source voltages in proportion to the difference between voltage levels of the first and second bit lines. Preferably, the first and second pull-up transistors are field effect transistors and the system further includes a diode serially connected between the, bit line and a reference potential.
According to the method disclosed herein high speed static random access memory operation is enhanced by isolating the capacitance of a bit line from the associated bit line pull-up device. Preferably the pull-up device functions as the sense amplifier load as well as the bit line current source to provide faster and simpler operation.